january 2001 ? 2001 fairchild semiconductor international nds8425 rev d (w) nds8425 single n-channel, 2.5v specified powertrench ? ? ? ? mosfet general description this n-channel 2.5v specified mosfet is produced using fairchild semiconductor?s advanced power trench process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance. these devices have been designed to offer exceptional power dissipation in a very small footprint package. applications ? dc/dc converter ? load switch features ? 7.4 a, 20 v. r ds(on) = 0.022 ? @ v gs = 4.5 v r ds(on) = 0.028 ? @ v gs = 2.7 v ? fast switching speed ? low gate charge (11nc typical) ? high performance trench technology for extremely low r ds(on) ? high power and current handling capability in a widely used surface mount package s d s s so-8 d d d g 4 3 2 1 5 6 7 8 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain-source voltage 20 v v gss gate-source voltage 8 v i d drain current ? continuous (note 1a) 7.4 a ? pulsed 20 power dissipation for single operation (note 1a) 2.5 (note 1b) 1.2 p d (note 1c) 1 w t j , t stg operating and storage junction temperature range -55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 50 c/w r jc thermal resistance, junction-to-case (note 1) 25 c/w package marking and ordering information device marking device reel size tape width quantity nds8425 nds8425 13?? 12mm 2500 units nds8425
nds8425 rev d (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain?source breakdown voltage v gs = 0 v, i d = 250 a 20 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 14 mv/ c i dss zero gate voltage drain current v ds = 16 v, v gs = 0 v v ds = 16 v,v gs = 0 v, t j =55 c 1 10 a i gssf gate?body leakage, forward v gs = 8 v, v ds = 0 v 100 na i gssr gate?body leakage, reverse v gs = ?8 v v ds = 0 v ?100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 0.40.891.5 v ? v gs(th) ? t j gate threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -3 mv/ c r ds(on) static drain?source on?resistance v gs = 4.5 v, i d = 7.4 a v gs = 4.5 v, i d = 7.4 a, t j =125 c v gs =2.7 v, i d =7.2a 15 21 19 22 31 28 m ? i d(on) on?state drain current v gs = 4.5 v, v ds = 5 v 20 a g fs forward transconductance v ds = 5 v, i d = 7.4 a 31 s dynamic characteristics c iss input capacitance 1098 pf c oss output capacitance 240 pf c rss reverse transfer capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 115 pf switching characteristics (note 2) t d(on) turn?on delay time 9 18 ns t r turn?on rise time 13 24 ns t d(off) turn?off delay time 26 42 ns t f turn?off fall time v ds = 15 v, i d = 1 a, v gs = 4.5 v, r gen = 6 ? 11 20 ns q g total gate charge 11 18 nc q gs gate?source charge 2.5 nc q gd gate?drain charge v ds = 10 v, i d = 7.4 a, v gs = 4.5 v 3.1 nc drain?source diode characteristics and maximum ratings i s maximum continuous drain?source diode forward current 1.9 a v sd drain?source diode forward voltage v gs = 0 v, i s = 1.9 a (note 2) 0.72 1.3 v notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a) 50/w when mounted on a 1 in 2 pad of 2 oz copper b) 105/w when mounted on a .04 in 2 pad of 2 oz copper c) 125/w when mounted on a minimum pad. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% nds8425
nds8425 rev d (w) typical characteristics 0 5 10 15 20 25 30 00.511.522.53 v ds , drain-source voltage (v) 3.5v 3.0v 2.5v 1.5v v gs = 4.5v 2.0v 4.0v 0.5 1 1.5 2 2.5 0 5 10 15 20 25 30 i d , drain current (a) v gs = 2.0v 3.5v 3.0v 4.0v 4.5 2.5v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) i d = 7.4a v gs = 4.5v 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 1234 v gs , gate to source voltage (v) i d = 7.4 a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 5 10 15 20 25 30 0.5 1.5 2.5 3.5 v gs , gate to source voltage (v) t a = -55 o c 25 o c 125 o c v ds = 5v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v sd , body diode forward voltage (v) t a = 125 o c 25 o -55 o c v gs = 0v figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. nds8425
nds8425 rev d (w) typical characteristics (continued) 0 1 2 3 4 5 024681012 q g , gate charge (nc) i d = 7.4a v ds = 5v 15v 10v 0 300 600 900 1200 1500 0.0 4.0 8.0 12.0 16.0 20.0 v ds , drain to source voltage (v) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.001 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage (v) dc 10s 1s 100ms 100 ja = 125 o c/w t a = 25 o c 10ms 1ms 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 t 1 , time (sec) single pulse r ja = 125 o c/w t a = 25 o c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 r ja (t) = r(t) + r ja r ja = 125 c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design. nds8425
soic(8lds) packaging configuration: figure 1.0 components leader tape 1680mm minimum or 210 empty pockets trailer tape 640mm minimum or 80 empty pockets soic(8lds) tape leader and trailer configuration: figure 2.0 cover tape carrier tape note/comments packaging option soic (8lds) packaging information standard (no flow code) l86z f011 packaging type reel size tnr 13" dia rail/tube - tnr 13" dia qty per reel/tube/bag 2,500 95 4,000 box dimension (mm) 343x64x343 530x130x83 343x64x343 max qty per box 5,000 30,000 8,000 d84z tnr 7" dia 500 184x187x47 1,000 weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 weight per reel (kg) 0.6060 - 0.9696 0.1182 f63tn label esd label 343mm x 342mm x 64mm standard intermediate box esd label f63tnr label sample f63tnlabel lot: cbvk741b019 fsid: fds9953a d/c1: d9842 qty1: spec rev: spec: qty: 2500 d/c2: qty2: cpn: n/f: f (f63tnr)3 f 852 nds 9959 soic-8 unit orientation f 852 nds 9959 pin 1 static dissipative embossed carrier tape
? 1998 fairchild semiconductor corporation dimensions are in millimeter pkg type a0 b0 w d 0 d1 e1 e2 f p1 p0 k0 t wc tc soic (8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 12.0 +/-0.3 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 10.25 min 5.50 +/-0.05 8.0 +/-0.1 4.0 +/-0.1 2.1 +/-0.10 0.450 +/- 0.150 9.2 +/-0.3 0.06 +/-0.02 p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 12mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 12mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed soic(8lds) embossed carrier tape configuration: figure 3.0 soic(8lds) reel configuration: figure 4.0 so ic -8 t ape and reel data, continued july 1999, rev. b
soic-8 (fs pkg code s1) 1 : 1 scale 1:1 on letter size paper di me n si o n s s h ow n be l ow a re in : inches [millimeters] part weight per unit (gram): 0.0774 soic-8 package dimensions september 1998, rev. a 9 ?2000 fairchild semiconductor international
trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher smart start? supersot?-3 supersot?-6 supersot?-8 fastr? globaloptoisolator? gto? hisec? isoplanar? microwire? optologic? optoplanar? pacman? pop? rev. g ? acex? bottomless? coolfet? crossvolt ? dome? e 2 cmos tm ensigna tm fact? fact quiet series? fast syncfet? tinylogic? uhc? vcx? ? ?
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